use iced_wgpu::wgpu; use iced_winit::Color; pub struct Scene { pipeline: wgpu::RenderPipeline, } impl Scene { pub fn new(device: &wgpu::Device) -> Scene { let pipeline = build_pipeline(device); Scene { pipeline } } pub fn clear<'a>( &self, target: &'a wgpu::TextureView, encoder: &'a mut wgpu::CommandEncoder, background_color: Color, ) -> wgpu::RenderPass<'a> { encoder.begin_render_pass(&wgpu::RenderPassDescriptor { label: None, color_attachments: &[wgpu::RenderPassColorAttachmentDescriptor { attachment: target, resolve_target: None, ops: wgpu::Operations { load: wgpu::LoadOp::Clear({ let [r, g, b, a] = background_color.into_linear(); wgpu::Color { r: r as f64, g: g as f64, b: b as f64, a: a as f64, } }), store: true, }, }], depth_stencil_attachment: None, }) } pub fn draw<'a>(&'a self, render_pass: &mut wgpu::RenderPass<'a>) { render_pass.set_pipeline(&self.pipeline); render_pass.draw(0..3, 0..1); } } fn build_pipeline(device: &wgpu::Device) -> wgpu::RenderPipeline { let vs_module = device.create_shader_module(&wgpu::include_spirv!("shader/vert.spv")); let fs_module = device.create_shader_module(&wgpu::include_spirv!("shader/frag.spv")); let pipeline_layout = device.create_pipeline_layout(&wgpu::PipelineLayoutDescriptor { label: None, push_constant_ranges: &[], bind_group_layouts: &[], }); let pipeline = device.create_render_pipeline(&wgpu::RenderPipelineDescriptor { label: None, layout: Some(&pipeline_layout), vertex: wgpu::VertexState { module: &vs_module, entry_point: "main", buffers: &[], }, fragment: Some(wgpu::FragmentState { module: &fs_module, entry_point: "main", targets: &[wgpu::ColorTargetState { format: wgpu::TextureFormat::Bgra8UnormSrgb, color_blend: wgpu::BlendState::REPLACE, alpha_blend: wgpu::BlendState::REPLACE, write_mask: wgpu::ColorWrite::ALL, }], }), primitive: wgpu::PrimitiveState { topology: wgpu::PrimitiveTopology::TriangleList, front_face: wgpu::FrontFace::Ccw, cull_mode: wgpu::CullMode::None, ..Default::default() }, depth_stencil: None, multisample: wgpu::MultisampleState { count: 1, mask: !0, alpha_to_coverage_enabled: false, }, }); pipeline }